---
id: 20260818-T0-14
title: "PPAPlace：用可微跨阶段目标优化芯片布局布线"
title_en: "PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement"
url: https://ai.daily.yangsir.net/daily/20260818-T0-14
issue_date: 2026-08-18
publish_date: 2026-08-17T04:00:00.000Z
category: research
source_name: "arXiv cs.LG (ML)"
source_url: https://arxiv.org/abs/2608.13790
---

# PPAPlace：用可微跨阶段目标优化芯片布局布线

芯片设计的新研究提出了一种名为PPAPlace的布局优化方法。传统方法主要优化线长（HPWL），但其与最终的芯片性能（PPA）关联度低。PPAPlace通过引入可微的跨阶段目标，直接优化布局对后续布线性能的影响。实验结果显示，该方法能在布局阶段更好预测并优化最终PPA，缩短芯片设计周期。

## English Version

**PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement**

Chip design research introduces PPAPlace, a method that uses differentiable cross-stage objectives to optimize macro placement. Unlike traditional methods that focus on wirelength, PPAPlace directly optimizes the impact on downstream performance, power, and area (PPA). It demonstrates a stronger correlation with final PPA, potentially reducing design cycle time.

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**来源**：[arXiv cs.LG (ML)](https://arxiv.org/abs/2608.13790)

**详情页**：https://ai.daily.yangsir.net/daily/20260818-T0-14

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