---
id: 20260923-T0-11
title: "PlaceReasoner-Beta：用推理做芯片宏单元布局，并给出评测基准"
title_en: "PlaceReasoner-Beta: Reasoning-Driven Macro Placement with New Benchmark"
url: https://ai.daily.yangsir.net/daily/20260923-T0-11
issue_date: 2026-09-23
publish_date: 2026-09-22T04:00:00.000Z
category: research
source_name: "arXiv cs.AI"
source_url: https://arxiv.org/abs/2609.21263
---

# PlaceReasoner-Beta：用推理做芯片宏单元布局，并给出评测基准

VLSI物理设计中的宏单元自动布局长期依赖人工设计的代理目标（如估算线长），效果有限。研究者发布PlaceReasoner-Beta，把布局问题改为由推理驱动，并配套推出基准测试，用于衡量模型在真实布局约束下的表现。相较以往只优化代理指标的做法，该工作强调可解释的推理过程与可复现的评测。对芯片设计团队而言，这意味着多了一个可对比的方案与评测集，便于判断推理式布局是否优于传统代理优化方法。

## English Version

**PlaceReasoner-Beta: Reasoning-Driven Macro Placement with New Benchmark**

Automated macro placement remains a core challenge in VLSI physical design, where existing methods mostly optimize hand-crafted proxy objectives such as estimated wirelength. Researchers released PlaceReasoner-Beta, a reasoning-driven approach to macro placement, along with a benchmarking suite for evaluating it under realistic layout constraints. Unlike prior proxy-only optimization, the work emphasizes interpretable reasoning and reproducible evaluation. For chip design teams, it offers both a comparable method and a benchmark to test whether reasoning-based placement beats traditional proxy optimization.

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**来源**：[arXiv cs.AI](https://arxiv.org/abs/2609.21263)

**详情页**：https://ai.daily.yangsir.net/daily/20260923-T0-11

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